| 摘要 |
PROBLEM TO BE SOLVED: To realize high speed data transfer even if an S-PCI bus side access occurs during a P-PCI bus side burst transfer. SOLUTION: During the burst transfer on a P-PCI bus 1a, even if an S-PCI bus 1b makes a transfer request, an assertion of a TRDY# signal to P-PCI side data transfer is delayed so that the next P-PCI side data transfer ends within eight clock cycles after the assertion of the TRDY# signal to P-PCI side data transfer, whereby the P-PCI side burst transfer is uninterrupted, and further P-PCI side data transfer is possible after S-PCI side data transfer. Even if S-PCI bus side access occurs during P-PCI bus side burst transfer, high speed data transfer can be realized. COPYRIGHT: (C)2004,JPO&NCIPI
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