发明名称 Texture engine memory access synchronizer
摘要 An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.
申请公布号 US6781588(B2) 申请公布日期 2004.08.24
申请号 US20010964802 申请日期 2001.09.28
申请人 INTEL CORPORATION 发明人 MARGITTAI GAVRIL;SPERBER ZEEV;MALKA GABI
分类号 G06T15/20;(IPC1-7):G06F13/18 主分类号 G06T15/20
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