发明名称 Processor system using synchronous dynamic memory
摘要 A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.
申请公布号 US2004143700(A1) 申请公布日期 2004.07.22
申请号 US20040752569 申请日期 2004.01.08
申请人 UCHIYAMA KUNIO;NISHII OSAMU 发明人 UCHIYAMA KUNIO;NISHII OSAMU
分类号 G06F15/78;G11C7/10;G11C8/12;G11C8/18;H04N7/26;H04N7/50;(IPC1-7):G06F12/00 主分类号 G06F15/78
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