| 摘要 |
A digital still camera includes a DRAM so that the DRAM is stored with pixel data having a Y, U or V component. A memory control circuit reads the pixel data out of the DRAM at a clock rate of 30 MHz, and writes it to SRAM. The memory control circuit then reads out the pixel data, that has been written from the SRAM to a first register, at a clock rate of 15 MHz and at a desired zoom magnification. An H/V interpolating circuit performs vertical interpolation and horizontal interpolation based on the data read out, and creates a zoom pixel. Since two pixels in a vertical direction is required to create one zoom pixel, the SRAM is formed with 2 lines of a memory area. Also, since only 1 line of data can read out of the DRAM at one time, the memory control circuit reads out the pixel data at a clock rate 2 times the value 15 MHz, i.e. 30 MHz.
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