发明名称 CLOCK SIGNAL GENERATION CIRCUIT AND DATA TRANSFER DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To generate an aperiodic clock signal with an simpler configuration, to reduce radiant noise emitted from a signal line, and to reduce generation of crosstalk between transferred signals. <P>SOLUTION: By inputting a reference clock signal C to delay elements 5, 6, 7, three stepwise-delayed delay clock signals X, Y, Z are generated. By a pseudo-random number generation circuit 9 operating at a rising edge of a delay inversion clock signal U formed by inverting the delay clock signal Z, a delay clock selection signal S randomly selecting a delay clock signal from the delay clock signals X, Y, Z is generated. A delay clock signal selector 10 generates a selection delay clock signal D according to the delay clock selection signal S. Data are transferred according to the selection delay clock signal D. <P>COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004192201(A) 申请公布日期 2004.07.08
申请号 JP20020357865 申请日期 2002.12.10
申请人 KONICA MINOLTA HOLDINGS INC 发明人 ABE MASAKAZU
分类号 G06F3/12;G06F1/04;G06F1/06;G06F1/10;H03K5/135;H03L7/00 主分类号 G06F3/12
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