发明名称 METHOD AND DATA PROCESSING SYSTEM FOR MICROPROCESSOR COMMUNICATION USING PROCESSOR INTERCONNECTED IN MULTIPROCESSOR SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. <P>SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store to a sector within each PCR and has continuous access to read PCR contents of itself. Each processor updates its exclusive sector within all of the PCRs using communication over a specialized bus, makes all other processors to be able to quickly see the change within the PCR data and bypasses a cache subsystem. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p>
申请公布号 JP2004192620(A) 申请公布日期 2004.07.08
申请号 JP20030389998 申请日期 2003.11.19
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 ARIMILLI RAVI KUMAR;CARGNONI ROBERT ALAN;WILLIAMS DEREK EDWARD;KENNETH LEE WRIGHT
分类号 G06F15/17;G06F9/46;G06F12/02;G06F13/14;G06F15/00;G06F15/16;G06F15/167;G06F15/173;G06F15/76;(IPC1-7):G06F15/173 主分类号 G06F15/17
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