Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps

摘要

A multi-level redistribution layer trace reduces current crowding in solder bumps of an integrated circuit package. A multi-level redistribution layer trace for an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in each of a plurality of electrically conductive layers and an I/O pad formed at a termination of the redistribution layer trace so that the I/O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers. The redistribution layer trace may also be slotted to divide current flow horizontally at the electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers.