FFT PROCESSOR TO REDUCE SIZE OF MEMORY

摘要

PURPOSE: An FFT(Fast Fourier Transform) processor to reduce a size of a memory is provided to reduce the size of the memory by installing a twiddle factor generator between a processor and the memory storing a twiddle factor. CONSTITUTION: An input buffer sequentially receives/stores the N data. The processor(104) comprises a complex number multiplier(202), a complex number adder(203), and a complex number subtracter(204), receives the data from the input buffer, and performs operation by using the twiddle factor. The first memory stores the data inputted through the processor. An address controller generates an I/O(Input/Output) address value of the first memory and the processor. A twiddle factor generator(201) receives the address value of the N bit from the outside, and generates/provides the twiddle factor needed for operation the FFT to the processor. The second memory outputs the stored value by receiving the address value from the twiddle factor generator.