发明名称 PROCESSOR DEVICE
摘要 PROBLEM TO BE SOLVED: To generate a highly versatile condition code by making a conversion mechanism converting a calculation result flag into the condition code variable. SOLUTION: An instruction set architecture specification part 9 specifies an instruction set architecture that is a conversion target in the conversion mechanism 3, and writes constitution data corresponding to the specified instruction set architecture into a changed value register 4. A constitution data decoder 3d reads a register value from the changed value register 4, decodes the constitution data, and outputs the decoded constitution data to a programmable logic device 3c. The programmable logic device 3c is reconstructed according to the constitution data, converts the calculation result flag into the condition code according to the instruction set architecture specified by the instruction set architecture specification part 9, and outputs the condition code to a condition code register 8. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004152201(A) 申请公布日期 2004.05.27
申请号 JP20020319234 申请日期 2002.11.01
申请人 MITSUBISHI ELECTRIC CORP 发明人 ITO TAKEHIRO
分类号 G06F9/308;(IPC1-7):G06F9/308 主分类号 G06F9/308
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