| 摘要 |
A sensing circuit for performing a direct read of a DRAM memory cell by using a high transfer ratio and a single ended read of a single bitline, wherein a limited number of memory cells are connected to the single bitline to limit the capacitance thereof to provide the high transfer ration. The direct read circuit includes four transistor devices, with three devices preferentially being nFETs. The direct read circuit provides a self-timed write back of data to a memory cell after the data is destructively read from the memory cell in a read operation, provides significant electrical power savings relative to prior art read circuits, as a read operation of a data 0 does not utilize any significant electrical power, and in a folded bitline architecture provides improved noise immunity as each non-active bitline shields an adjacent active bitline.
|
