| 摘要 |
A hybrid multiple redundant computer system having redundant input modules, central processor modules, and output modules operating in parallel, where output circuits within each output module are connected to associated microcontrollers, such that, a first output circuit is connected to a first and a third microcontroller, a second output circuit is connected to a second and the first microcontroller, and a third output circuit is connected to the third and the second microcontroller; each output module further comprising watchdog controllers for detecting faults within the microcontrollers or central processing modules, where the watchdog controllers produce alarm signals upon detection of a failure within these components; the output circuits further including means for providing a 2-of-3 vote among data produced by three central processor modules if alarm signals are not activated and for reverting to a 2-of-2 and 1-of-1 vote in the presence of one and two faulty components respectively. The microcontrollers further including fault diagnostic and fault recovering means to provide correct system outputs in the presence of up to at least two faulty components in the output circuits.
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