| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a half rate linear phase detector having a large timing margin. <P>SOLUTION: A circuit is designed to supply an input data signal and an output indicating a clock signal. The circuit has a means for performing a discrete re-timing process of odd number and even number of the input data signal and for supplying an even number re-timing process data signal and an odd number re-timing process data signal, first logic synthesizing means for synthesizing the data signal, the clock signal, the inverted clock signal, the even number retimed signal, and the odd number retimed signal to output a logic combined signal, and second logic synthesizing means for supplying the output after combining the logic combined signal. <P>COPYRIGHT: (C)2004,JPO</p> |
