| 摘要 |
PLL APPARATUS (16) FOR GENERATING AN OSCILLATORY SIGNAL (S5) PHASE LOCKED TO A COMPONENT (S2) OF A FURTHER SIGNAL (S1) COMPRISES A VARIABLE OSCILLATOR (26) FOR GENERATING THE OSCILLATORY SIGNAL (S5) AND A SOURCE (12) OF THE FURTHER SIGNAL (S1). A PHASE DETECTOR (22, 30) RESPONSIVE TO THE OSCILLATORY SIGNAL (S5) AND TO THE COMPONENT OF THE FURTHER SIGNAL (S2), PROVIDES A PHASE ERROR SIGNAL (S9) WHICH IS COUPLED TO THE VARIABLE OSCILLATOR (26) VIA A LIMITER (50). CIRCUIT MEANS (44) ARE PROVIDED FOR CONTROLLING THE LIMITING LEVEL OF THE LIMITER. THE DUAL LIMITING SUBSTANTIALLY IMPROVERS THE LOOP NOISE TOLERANCE AND REDUCES THE LOOP SENSITIVITY TO OCCASIONAL PHASE REVERSALS OF THE COMPONENT OF THE FURTHER SIGNAL. ADDITIONAL ENCHANCEMENTS TO LOOP STABILITY AND NOISE IMMUNITY ARE PROVIDED BY AN UNLOCK DETECTOR (808, 812, 814) WHICH DETECTS AND TOTALIZES PHASE ROTATIONS IN A SELECTED AREA OF A PHASE PLANE AND BY A PHASE WRAP DETECTOR (804) WHICH MAINTAINS A LOCK INDICATION DURING PHASE ANGLE.
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