发明名称 Non-volatile memory and method with reduced source line bias errors
摘要 Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. Typically with each pass, the given demarcation current value progressively converges to the breakpoint current value for a convention single pass sensing. In this way, sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells.
申请公布号 US2004057287(A1) 申请公布日期 2004.03.25
申请号 US20020254830 申请日期 2002.09.24
申请人 SANDISK CORPORATION 发明人 CERNEA RAUL-ADRIAN;LI YAN
分类号 G11C7/06;G11C11/56;G11C16/26;G11C16/28;G11C29/02;(IPC1-7):G11C16/06 主分类号 G11C7/06
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