Information processing device for multiple instruction sets with reconfigurable mechanism

摘要

Disclosed here is a mechanism provided in an instruction translator for translating an intermediate code (Java bytecode) to an instruction string so as to be interpreted by an instruction execution block corresponding to various upgraded versions of a virtual machine (computer) (VM). Each instruction included in the first instruction group of the intermediate code is translated to an instruction to be interpreted by hardware while each instruction included in the second instruction group is translated by software. The information processing device is configured so that the intermediate code has a storage area for storing information for denoting which of the first and second instruction groups includes the intermediate code. Thus, instruction translation can be made by the same hardware to cope with various upgraded versions of a VM if the values are set in the setting register. In addition, the hardware is not required to be modified to translate instructions even when the VM version is upgraded.