| 摘要 |
PURPOSE: A method for manufacturing a multi-layered metal line of a semiconductor device using a dual damascene process and a structure thereof are provided to be capable of preventing the dishing and erosion phenomenon of a lower metal line for stably carrying out a CMP(Chemical Mechanical Polishing) process at an upper metal line by using a polishing stop layer. CONSTITUTION: After forming the first interlayer dielectric(100) at the upper portion of a semiconductor substrate, a trench or a via hole is formed by selectively etching the first interlayer dielectric. A polishing stop layer(106) is formed on the entire surface of the resultant structure. After carrying out a conductive layer gap-fill process at the upper portion of the resultant structure, a lower metal line(108a) or a via(108b) is formed by carrying out a CMP process at the conductive layer until the surface of the polishing stop layer is exposed. After forming the second interlayer dielectric at the resultant structure, a trench is formed by selectively etching the second interlayer dielectric. Then, a plurality of upper metal lines(116a,116b) are formed at the resultant structure by filling the trench using a conductive layer.
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