| 摘要 |
A method for clustered pattern generation maintains high fault coverage of a circuit under test while it reduces the amount of test data to store by using clusters of correlated test patterns. A test pattern generator stores only a small number of center test vectors which serve as centers of clusters. The generator applies each center test vector to a circuit under test multiple times. However, every time the center vector is shifted into the circuit, some of its positions are complemented. The cluster may have a number of spheres which correspond to test vectors derived with various diffraction probabilities and computed to maximize fault coverage, minimize the total number of clusters, and reduce the test application time. The method also encodes several partially specified center test vectors in scan path using the polarity between scan cells, scan order and waveform generators controlling scan inputs.
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