发明名称 |
Lock detector for phase locked loops |
摘要 |
A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.
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申请公布号 |
US2003197565(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
US20030435446 |
申请日期 |
2003.05.09 |
申请人 |
TAN LOKE KUN;ETEMADI FARZAD;YUEN DENNY;TSAI SHAUHYURN (SEAN) |
发明人 |
TAN LOKE KUN;ETEMADI FARZAD;YUEN DENNY;TSAI SHAUHYURN (SEAN) |
分类号 |
H03L7/095;H03L7/107;(IPC1-7):H03L7/00 |
主分类号 |
H03L7/095 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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