发明名称 MULTIPLE OUTPUT SYSTEM USING VARIABLE CLOCK
摘要 PURPOSE: A multiple output system using a variable clock is provided to support various output formats at the same time by using the least variable clock source in a system compensating errors of input and output periods by using variable clocks. CONSTITUTION: A synchronous control signal generating unit(100) locks synchronization of a synchronous signal of a video signal with video signals inputted through bit streams for generating synchronous control signals of a plurality of output video formats. A variable clock source unit(200) varies an output frequency according to the generated synchronous control signals to synchronize and display the input video signal and the output video signal, so that the variable clock source unit outputs a control synchronous signal supporting operational clocks of the plurality of output video formats. A PLL(Phase Locked Loop)(300) synthesizes the operational clocks to match synchronization of the input video signal and the output video signal according to the varied control synchronous signal.
申请公布号 KR20030082279(A) 申请公布日期 2003.10.22
申请号 KR20020020933 申请日期 2002.04.17
申请人 LG ELECTRONICS INC. 发明人 AHN, JIN HO;HAN, DONG IL
分类号 H04N7/01;(IPC1-7):H04N7/01 主分类号 H04N7/01
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