发明名称 System and method for frame accurate splicing of compressed bitstreams
摘要 A system for performing frame accurate bitstream splicing includes a first pre-buffer, a second pre-buffer, a seamless splicer, and a post-buffer. The system also includes a time stamp extractor, a time stamp adjuster, and a time stamp replacer for timing correction. The first and second pre-buffers are input buffers to the seamless splicer, and the post-buffer is coupled to the output of the seamless splicer. The seamless splicer receives the two streams via the first and second pre-buffers and produces a single spliced bitstream at its output in response to the cue tone signal. The seamless splicer provides the first bitstream, then re-encodes portions of the first and second bit streams proximate the splicing points (both the exit point and the entry point), and then switches to providing a second bitstream. The seamless splicer also performs rate conversion on the second stream as necessary to ensure decoder buffer compliance for the spliced bitstream. The present invention also includes a method for performing bitstream splicing comprising the steps of: determining a splicing point switching between a first bitstream and a second bitstream, determining whether the second bitstream has the same bit rate as the first bitstream, converting the rate of the second bitstream if it is not the same as the bit rate of the first bitstream, and re-encoding picture proximate the splicing point.
申请公布号 US6611624(B1) 申请公布日期 2003.08.26
申请号 US19980173708 申请日期 1998.10.15
申请人 CISCO SYSTEMS, INC. 发明人 ZHANG JI;TSE YI TONG
分类号 H04N7/24;H04N7/26;(IPC1-7):G06K9/36;H04N7/12;H04J3/00 主分类号 H04N7/24
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