| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an image data receiving apparatus capable of being operated synchronously with a system clock of an encoder side (server side) even in the case of using a decoder on which no clock reference type PLL circuit is mounted. <P>SOLUTION: The frequency of the system clock outputted from a 27 MHz clock control circuit 226 being a reference of a decoder LSI 224 is fine-adjusted so that a data residual amount is within a reference range in response to a state that a data residual amount of an FIFO memory 222 provided to a pre- stage of the decoder LSI 224 is increased/decreased. Thus, the frequency of the system clock is matched with the frequency of a system clock at the encoder side. As a result, overflow or underflow of the buffer to be caused in the dissidence between the processing clocks of the encoder and the decoder can be avoided and a decoded image can be prevented from being frozen or skipped. <P>COPYRIGHT: (C)2003,JPO |
