DIRECT CONVERSION RECEIVER AND DC OFFSET REDUCING METHOD

摘要

A deciding part (18) and a gain variation determining part (9) detects a time interval during which the DC component offset of internal circuits of a direct conversion receiver may increase beyond a permissible value due to AGC operation. During this time interval, the cutoff frequencies of high pass filters (12a-12d) are caused to be higher than those of their normal operations, thereby causing the transient responses of signals having passed through those filters to rapidly converge. At the same time, the operational timings of a reception power measuring part (16), a gain calculating part (22), a gain control part (23) and a circuit power supply control part (24) that constitute an AGC loop are finely controlled, thereby preventing an increase of the DC offset and ensuring a stable circuit operation. This can accomplish a further miniaturization of and a power consumption reduction of a CDMA receiver using this direct conversion receiver.