| 摘要 |
PROBLEM TO BE SOLVED: To enhance impedance matching accuracy in programmable impedance circuit technology. SOLUTION: A filter signal fil outputted from a buffer size determining circuit 21 along with a buffer size control signal Pz is synchronized with a clock signal CK for controlling data output thus generating a filter signal fck. Update of buffer size is prohibited during an interval when the filter signal fck synchronized with the clock signal CK is L and the buffer size is updated after the filter signal fck becomes H thus updating the buffer size in synchronism with the clock signal CK. COPYRIGHT: (C)2003,JPO
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