ITERATIVE DECODING RESTRICTION APPARATUS USING SATURATED BIT VALUE AND TURBO DECODING SYSTEM USING THE SAME

摘要

PURPOSE: An iterative decoding restriction apparatus using saturated bit value and a turbo decoding system using the same are provided to reduce the average number of iterative decoding by restricting the iterative decoding number variably. CONSTITUTION: According to the iterative decoding restriction apparatus, the first LLR(Log Likelihood Ratio) processing unit judges a time point when a saturated bit coefficient value does not increase any more by counting the number of maximum saturation of the first decoding result(LLR0) of a MAP(Maximum A Posteriori) decoder. The second LLR processing unit judges a time point when the saturated bit coefficient value does not increase any more by counting the number of maximum saturation of the second decoding result of the MAP decoder. An iterative decoding stop unit outputs an iterative decoding stop signal(314) of the MAP decoder, according to the judgement result of the first and the second LLR processing unit.