发明名称 |
Power modeling methodology for a pipelined processor |
摘要 |
A method for modeling the power behavior of a pipelined processor has been developed. The method uses a power model integrated into a cycle accurate simulator. To create the power model, design blocks of the processor are divided into sub-blocks. Power modeling equations for each sub-block are developed by collaboration between the sub-block circuit designer and the simulator developer, using activity information relevant to the sub-block that is available in the simulator model. Each equation is calculated multiple times with different sets of power parameters to represent varying power conditions. Every simulation cycle, sub-block power is summed to generate full-chip power for multiple power conditions.
|
申请公布号 |
US2003110020(A1) |
申请公布日期 |
2003.06.12 |
申请号 |
US20010010239 |
申请日期 |
2001.12.07 |
申请人 |
BLATT MIRIAM G.;KONGETIRA POONACHA;GREENHILL DAVID J.;GANESAN VIDYASAGAR |
发明人 |
BLATT MIRIAM G.;KONGETIRA POONACHA;GREENHILL DAVID J.;GANESAN VIDYASAGAR |
分类号 |
G06F9/455;G06F17/50;G06G7/54;(IPC1-7):G06G7/54 |
主分类号 |
G06F9/455 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|