发明名称 LEVEL 2 PROCESSING MULTIPLEXER AND MULTIPLEXING METHOD FOR No.7 SIGNAL SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a level 2 processing multiplexer and a level 2 multiplexing method capable of increasing a multiple number of a level 2 processing inaptitude for multiplexing while preventing deterioration in the firmware processing capability. SOLUTION: The level 2 processing of the No.7 signal system is configured to be implemented by a protocol processing section applying protocol processing to a signal unit (SU) and a signal unit processing section that processes the signal unit received from the protocol processing section in a form of a frame multiplexed signal and uses sequence number (SN) of the signal unit to autonomously and periodically generate a fill-in signal unit (FISU) by means of hardware so as to realize multiplexing by reducing the firmware processing. A link state signal unit (LSSU) and a meaningful signal unit (MSU) of the level 2 processing multiplexer are provided with a parity error detection function, and on the occurrence of a fault, the firmware processing can be reduced with an added function of transmitting a transmission signal whose error check code is brought into a virtual fault allows an opposite station to be able to abort erroneous data by error check/synchronization control.
申请公布号 JP2003115934(A) 申请公布日期 2003.04.18
申请号 JP20010311054 申请日期 2001.10.09
申请人 NEC CORP 发明人 SHIMURA MIKIKO
分类号 H04L1/00;H04J3/00;H04M7/06;H04Q11/04;(IPC1-7):H04M7/06 主分类号 H04L1/00
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