发明名称 Dynamic precharge decode scheme for fast DRAM
摘要 A dynamic random access memory includes first and second address generators, subarrays, an address decode path and a precharge activation path, wherein the precharge activation path and the address decode path are matched. The first address generator identifies a word and a column address. The second address generator identifies a subarray address. The subarrays include a number of cells for storing data. The address decode is configured to transmit address and other information while the precharge activation path is configured to transmit a precharge activation signal. In a preferred embodiment, an event during an active phase process, such as a sense amplifier set signal initiation, initiates the precharge phase process.
申请公布号 US6510091(B1) 申请公布日期 2003.01.21
申请号 US20010918830 申请日期 2001.08.01
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BRACERAS GEORGE M.;PILO HAROLD
分类号 G11C7/12;G11C7/22;G11C11/4076;G11C11/4094;(IPC1-7):G11C7/00 主分类号 G11C7/12
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