发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit that has a short lock time from a dead lock state restored to a locks state. SOLUTION: The phase-locked loop circuit is provided with a reference signal input terminal 1, a phase comparator 2, a charge pump 3, a loop filter 4, a dead lock processing circuit 5, a voltage-controlled oscillator 6, an oscillation output terminal 7, and a frequency divider 8 and switches a control voltage of the voltage-controlled oscillator in a dead locks state from a loop filter output into a dead-lock release voltage.
申请公布号 JP2003018004(A) 申请公布日期 2003.01.17
申请号 JP20010195436 申请日期 2001.06.27
申请人 NEC MICROSYSTEMS LTD 发明人 FUKUDA KOJI
分类号 H03L7/10;H03L7/095;H04L7/033 主分类号 H03L7/10
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