| 摘要 |
PURPOSE: An apparatus for detecting a minimum value, a maximum value, and a last value is provided to reduce the load of a DSP(Digital Signal Processor) and simultaneously progress an other work in the DSP by detecting the maximum value, the minimum value, and the last value and transmitting only the detected values to the DSP in a separate hardware. CONSTITUTION: A DSP(110) outputs an address and data, and outputs a time interval for obtaining a maximum value, a minimum value, and a last value and an acquisition start command. An A/D converter(120) outputs sampled data. An FPGA(Field Programmable Gate Array)(130) decodes the address outputted from the DSP(110), receives the time interval and a command about on/off, detects a maximum value, a minimum value, and a last value among data inputted from the A/D converter(120), and outputs the maximum value, the minimum value, and the last value to the DSP(110).
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