发明名称 Clocked pass transistor and complementary pass transistor logic circuits
摘要 A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.
申请公布号 US2002191460(A1) 申请公布日期 2002.12.19
申请号 US20020218511 申请日期 2002.08.15
申请人 FORBES LEONARD 发明人 FORBES LEONARD
分类号 H03K19/096;H04L25/02;(IPC1-7):H03K19/096 主分类号 H03K19/096
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