| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory in which short circuit defect can be detected in a short time. SOLUTION: When a test signal TE is made to be 'H', all sub-arrays 10k are selected by an OR31k , and all word lines WLi are made to be a non-selection state by an AND32i . Also, all drain lines DL in the sub arrays 10 are connected to a power source potential MCD by OR34, 35, and all source lines SL are connected to data lines DTL through bit lines BL by an OR36j . Further, the data lines DTL are connected to a ground potential GND through a NMOS 24. At this time, as all memory cells 11 are in a non-selection state, when short circuit defect is not caused, a short circuit current is not generated independently of contents of the memory cells 11. If the drain lines DL and the source liens SL are short-circuited, current is made to flow from the power source potential MCD to the ground potential GND through the short circuit point.</p> |
