| 摘要 |
PURPOSE: A fabrication method of MML(Merged Memory and Logic) devices is provided to simplify manufacturing processes and to reduce manufacturing costs by using two-step photolithographic processes. CONSTITUTION: Gate electrodes(3a,3b,3c) are formed a cell region(MC), a peripheral region(MP) and a logic region(L) of a semiconductor substrate(1), respectively. A nitride layer(5) is covered on the gate electrodes and an interlayer dielectric(6) is formed on the nitride layer(5). A first spacer(5a) is formed at both sidewalls of the gate electrode located at an NMOS formation region by selectively etching the interlayer dielectric(6) and the nitride layer(5) using a first photoresist pattern for exposing the NMOS formation region of the peripheral region(MP) and the logic region(L). An N-type source/drain region(9a) is formed in the substrate. A second spacer(5b) is formed at both sidewalls of the gate electrode located at a PMOS formation region by selectively etching the interlayer dielectric(6) and the nitride layer(5) using a second photoresist pattern for exposing the PMOS formation region of the peripheral region(MP) and the logic region(L). Then, a P-type source/drain region(9b) is formed in the substrate.
|
