| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable realizing block erasure by cutting off a memory cell current of a defective bit line after redundancy replacing and suppressing reduction of a source line potential in block erasure. SOLUTION: This device is provided with a memory cell array 1 in which bit lines BL1, BL2-BLj are shared by a plurality of blocks BLKa, BLKb and which has a redundant bit line BLj, a column select-gate 5 connected to a drain node of a memory cell through a bit line, a sense amplifier circuit 6 and a write-in circuit 7 connected to the column select-gate 5, a row decoder 2 connected to a gate of a memory cell, a positive voltage applying selecting circuit 9 for fixing a bit line to a specific positive potential, a positive voltage applying selection control circuit 10 for controlling the positive voltage applying selecting circuit 9, and a positive voltage generating circuit 3.</p> |
