| 摘要 |
PROBLEM TO BE SOLVED: To provide an NAND cell-type EEPROM that can reduce the element isolation region between NAND cells, and can improve integration. SOLUTION: The NAND cell is composed by connecting a plurality of memory cells in series. In the memory cell, a charge accumulation layer and a control gate are laminated on a semiconductor substrate while an insulating film is being sandwiched. In the EEPROM where the NAND cells are arranged in a matrix, a bit line 1 is arranged in the direction that orthogonally crosses a control gate CG used as a word line, the drain side of each NAND cell is connected to the bit line 1 by a bit line contact 2 via a selection transistor 5, and the adjacent bit line contacts 2 in each NAND cell are alternately shifted in the bit line direction.
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