PURPOSE: A synchronous DRAM(Dynamic Random Access Memory) device is provided to reduce an occupied area of a refresh counter by using a counter shared by a plurality of registers. CONSTITUTION: One counter(100) is shared by two registers(140). The first register corresponds to the first bank memory array. The second register(140) corresponds to the second bank memory array. A refresh controller(34) is used for reading a refresh command applied from the outside. The read data are applied to the counter(100). The first and the second registers(140) are selectively operated according to bank address information. The first register loads the stored low address information to the counter(100). The counter(100) generates a low address for refresh by using the stored low address information. The low address for refresh is provided to a low multiplexer(46). The low address is used for selecting word lines of the first bank memory array through a low address buffer and a low decoder.
