发明名称 Multiprocessor cache coherence management
摘要 A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally accessible by the processor and remotely accessible via the network by all other processors. A home directory records states and locations of data blocks in the memory unit. A prediction facility that contains reference history information of the data blocks predicts a next requester of a number of the data blocks that have been referenced recently. The next requester is informed by the prediction facility of the current owner of the data block. As a result, the next requester can issue a request to the current owner directly without an additional hop through the home directory.
申请公布号 US2002144063(A1) 申请公布日期 2002.10.03
申请号 US20010823251 申请日期 2001.03.29
申请人 PEIR JIH-KWON;LAI KONRAD 发明人 PEIR JIH-KWON;LAI KONRAD
分类号 G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/08
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