LAYOUT METHOD FOR SEMICONDUCTOR DEVICE

摘要

PURPOSE: A layout method for a semiconductor device is provided not only to prevent electrostatic discharge and latch up in a high-integrated chip, but also to reduce the size of the chip. CONSTITUTION: In the method, a cell array is disposed within a main chip and a periphery circuit is disposed around the cell array. Pads(20), each acting as an input/output pad, are disposed between the periphery circuit and the edge of the chip. Transistors for electrostatic discharge protection are disposed between the pads(20) and the edge of the chip. The transistors are connected to the pads(20), respectively. For latch up protection, an n-well guard ring(60) is disposed below the pads(20). Since the guard ring(60) is underneath the pads(20), the size of the chip can be reduced.