| 摘要 |
<p>1277714 Pulse generators NORTH AMERICAN ROCKWELL CORP 18 Jan 1971 [15 June 1970] 2395/71 Heading H3T A pulse generator, Fig. 1, produces trains of output pulses at A and B (Fig. 4, not shown) which are related in frequency and in phase (##) and which are logically combined in Fig. 3 to produce trains of single width clock pulses # 1 , # 3 and trains of double width pulses # 1+2 , # 3+4 all trains being related in frequency and in phase. The generator, Fig. 1, is an oscillator in which F.E.T. inverters 29, 30, 31, 32, 37 are coupled in a ring through respective RC delay circuits, where the R is a F.E.T. device 19-23 having its value controlled by a voltage at 18. This voltage is maintained substantially independent of variations in -V by F.E.T. 14 and R13; and changes in frequency due to temperature induced changes in R19-R23 are compensated by R13 changing to adjust the control voltage at 18. Five outputs (each phase shifted by ## = 1/5 of half a period of the oscillation) are available, CDEFG (Fig. 2, not shown) of which C goes to a driver circuit producing A; while D and F go to an exclusive OR gate comprising NOR 52, AND 53, NOR 54 and a driver circuit to produce B. B is twice the frequency of A and starts at each edge of D, whereby the delay (##) occurs between each A edge and the next B positive edge. The logic circuit, Fig. 3, has four channels receiving A, B, A, B. For example, NOR 69 responds when A or B is positive (A or B negative, Fig. 4, not shown) to take F.E.T. 75 gate negative and pass the negative level to F.E.T. 78; this makes # 1 negative, and bootstrap C79 assists switching. # 1 is positive (earth) only when A and B are positive, so that F.E.T. 75 is off and F.E.T. 77 is on to discharge capacitances, and F.E.T. 74 is on. Similarly # 3 is produced from A and B. AND gates 88, 97 receive B and drive NOR gates 90, 99 respectively receiving A and A; and both NOR gates drive circuits similar to the other channels with the addition of a latching feedback to the AND gates 88, 97 which maintain the outputs at 65, 66 at earth until the end of the respective A or A pulse, thus generating # 1+2 and # 3+4 . All four clock pulses now have the ## delay to allow for response times in the circuits being driven. A bootstrap inverter F.E.T. (44, Fig. 6, not shown) for use as the inverter 40 of Fig. 1 has a drain load consisting of a further F.E.T. (43) with a capacitor between its source and gate and a resistor-connected F.E.T. 42 between its gate and drain, the source (of 43) being connected to the drain of the inverter F.E.T. (44).</p> |
