发明名称 Method of testing a semiconductor integrated circuit and method and apparatus for generating test patterns
摘要 There is provided an apparatus and a method for automatically generating patterns including a pattern applied for a path that influences crosstalk to a measurement path, in a delay test using a scan path to make measurement of the effect of the path that influences crosstalk to the measurement path possible. An adjacent path extraction process 102 is performed on the basis of layout information on a semiconductor integrated circuit so as to extract information on a path that influences crosstalk, with reference to crosstalk information, a measurement path extraction process (106) is performed, so that information on an aggressor path that influences crosstalk to the measurement path of a combinational circuit between flip-flops that constitutes the scan path is generated, and then, on the basis of circuit information (108), and information (107) on the measurement path and the aggressor path, a Delay_test ATG (109) generates delay test patterns (110), including a pattern for outputting a signal for measuring a delay from a flip-flop associated with the measurement path and a pattern for outputting a signal that influence crosstalk to the measurement path from a flip-flop associated with the aggressor path.
申请公布号 US2002124218(A1) 申请公布日期 2002.09.05
申请号 US20020083447 申请日期 2002.02.26
申请人 KISHIMOTO KAZUNORI 发明人 KISHIMOTO KAZUNORI
分类号 G01R31/28;G01R31/3181;G01R31/3183;H01L21/822;H01L27/04;(IPC1-7):G01R31/28;G06F11/00 主分类号 G01R31/28
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