| 摘要 |
A semiconductor memory device including a memory cell for holding charge of first cell information or second cell information, a word line connected to the memory cell for supplying the memory cell with word line voltage, a bit line connected to the memory cell for conveying charge corresponding to the first or second cell information, a dummy cell connected to the bit line for supplying the bit line with complementary charge, and a dummy word line connected to the dummy cell for supplying the dummy cell with dummy word line voltage. The first cell information is read based on the charge conveyed to the bit line from the memory cell when the word line is activated, and the second cell information is read based on the complementary charge supplied to the bit line from the dummy cell when the dummy word line is activated.
|
