| 发明名称 |
Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices |
| 摘要 |
The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M-Si or M-Si-Ge alloy, where M is Co, Ni or CoNi, and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
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| 申请公布号 |
US2002115262(A1) |
申请公布日期 |
2002.08.22 |
| 申请号 |
US20010791024 |
申请日期 |
2001.02.21 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CABRAL CYRIL;CARRUTHERS ROY ARTHUR;CHAN KEVIN K.;COHEN GUY M.;GUARINI KATHRYN WILDER;HARPER JAMES M.E.;LAVOIE CHRISTIAN;SOLOMON PAUL M. |
| 分类号 |
H01L21/285;(IPC1-7):H01L21/76;H01L21/31;H01L21/44;H01L21/469 |
主分类号 |
H01L21/285 |
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