CHIP SCALE PACKAGE AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A chip scale package(CSP) is provided to improve a degree of freedom for disposing solder lands while an ideal bonding process is performed, by directly bonding a semiconductor chip having a solder bump to a via hole on a metal down flexible tape while using inexpensive solder paste or flux. CONSTITUTION: The via hole is formed on the metal down flexible tape. A circuit interconnection and a solder ball land connected to the via hole are formed on the bottom surface of the metal down flexible tape. The via hole of the metal down flexible tape is filled with solder paste. The semiconductor chip(1) is attached to the meal down flexible tape. The solder bump is formed on a bonding pad of the semiconductor chip. Molding resin encapsulates the semiconductor chip.