A semiconductor integrated circuit comprising a normal circuit and a redundancy circuit in which irremediable wirings are arranged contiguously to each other while arranging a plurality of remediable first wirings and a plurality of irremediable second wirings constituting the normal circuit in the same direction in the same wiring layer.
申请公布号
WO02061839(A1)
申请公布日期
2002.08.08
申请号
WO2001JP09203
申请日期
2001.10.19
申请人
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD.;ISHIMATSU, MANABU;INOUE, YOSHIHIKO;YOSHIOKA, HIROSHI;SUZUKI, MASAHITO