发明名称 |
Method and system for formal verification of a circuit model |
摘要 |
The present invention provides a method and system for comparing a pair of circuit models without the need for performing a false negative check when cut-points are introduced. An exemplary method includes generating a BDD for each of a plurality of signals of each circuit model from an initial cut-point frontier towards an output of each circuit model until a BDD of one of the plurality of signals reaches a predetermined maximum size, selecting a new cut-point signal frontier, and generating a normalized function for each cut-point signal on the new cut-point frontier of each circuit model.
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申请公布号 |
US2002108093(A1) |
申请公布日期 |
2002.08.08 |
申请号 |
US20000734380 |
申请日期 |
2000.12.11 |
申请人 |
INTEL CORPORATION |
发明人 |
MOONDANOS JOHN;SEGER CARL J.;HANNA ZIYAD;KAISS DAHER ADIL |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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