发明名称 MEMORY DEVICE COMPRISING COLUMN ADDRESS DECODER DEDICATED FOR READ AND WRITE
摘要 PURPOSE: A memory device comprising a column address decoder dedicated for read and write is provided, which maximizes operation frequencies of read and write by using two column address decoders for read and write separately. CONSTITUTION: According to a memory array including a column address decoder, the column address decoder is divided into a column address decoder(YDEC(RD)) dedicated for read and a column address decoder(YDEC(WT)) dedicated for writing. A proceeding direction of an address(Addr.) and a proceeding direction of data(GDB) become equal by the column address decoder dedicated for read during a read operation. And a proceeding direction the address and a proceeding direction of data become equal by the column address decoder dedicated for write.
申请公布号 KR20020058993(A) 申请公布日期 2002.07.12
申请号 KR20000087138 申请日期 2000.12.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, GWAN WON;LEE, SEONG HUN
分类号 G11C8/10;(IPC1-7):G11C8/10 主分类号 G11C8/10
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