| 摘要 |
PURPOSE: A formation method of metal interconnections of semiconductor devices is provided to improve a characteristic and a reliability by forming a planarized metal interconnection using an electrolysis polishing. CONSTITUTION: After forming an interlayer dielectric(35) on a semiconductor substrate(31) having a defined structure, a via contact hole is formed to expose the first metal interconnection(33) and trenches are simultaneously formed by selectively etching the interlayer dielectric(35). Then, the exposed first metal interconnection(33) is cleaned through the via contact hole and a barrier metal(41) is formed on the resultant structure. Then, a copper layer is filled into the contact hole and the trenches using an electrolytic plating and the copper layer is then planarized by an electrolytic polishing. So, a planarized second metal interconnection(45) is formed by additionally performing a CMP(Chemical Mechanical Polishing) on the exposed barrier metal(41) and a capping layer(47) is formed on the entire surface of the resultant structure.
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