VITERBI DECODER AND DECODING METHOD THEREOF

摘要

PURPOSE: A viterbi decoder and a decoding method thereof are provided, which are not affected by a length of a constraint length while constituting a hardware, and simplifies a decoding process and a hardware size while performing a decoding. CONSTITUTION: A memory(100) stores an optimum register state value generated per step of an encoding. An optimum state discrimination part(400) discriminates a position of a register whose state is optimum in each step among the state values of the register stored in the memory and then outputs its position value. The first MUX(200) selects a state value of a position corresponding to the position value being output from the optimum state discrimination part among the state values of the registers per step being output from the memory by being synchronized to a system clock. And a storing part(LIFO, Last Input First Output)(300) stores the selected state values in sequence, and then outputs decoded data.