发明名称 |
Method of forming a floating gate self-aligned to STI on EEPROM |
摘要 |
A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.
|
申请公布号 |
US6403494(B1) |
申请公布日期 |
2002.06.11 |
申请号 |
US20000638300 |
申请日期 |
2000.08.14 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
CHU WEN-TING;KUO DI-SON;YEH JACK;HSIEH CHIA-TA;CHANG CHUAN-LI |
分类号 |
H01L21/8247;H01L27/115;(IPC1-7):H01L21/00 |
主分类号 |
H01L21/8247 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|