发明名称 Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
摘要 A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.
申请公布号 US2002069396(A1) 申请公布日期 2002.06.06
申请号 US20010896059 申请日期 2001.06.29
申请人 ZENASIS TECHNOLOGIES, INC. 发明人 BHATTACHARYA DEBASHIS;BOPPANA VAMSI;ROY RABINDRA K.;ROY JAYANTA
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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