DLL AND METHOD FOR LOCKING IT USING MULTIPLE PHASE DETECTOR

摘要

A delay lock loop, in accordance with the present invention, includes a plurality of phase detectors (106) each receiving a first clock signal (Ref Clock) and a second clock signal (FB Clock). Each phase detector includes a specified delay range for detecting phase differences between the first and second clock signals in that range. A delay line (104) includes an input and an output. The first clock signal is received at the input, and the second clock signal includes a delayed first clock signal. An amount of delay is applied to the first clock signal, which is adjusted in the delay line in accordance with control signals of the phase detectors.